How to Run a Cycle Mode (DSM=yes) for CORTEX-M0 Processor?

The Cortex-M0 processor supports a debug mode called Cycle Mode or Data Streaming Mode (DSM) that allows real-time data to be streamed off-chip while the processor continues to execute instructions. This is useful for debugging and profiling applications by observing the processor’s state without halting execution. Enabling DSM mode is done by setting the DSM bit in the Debug Halting Control and Status Register (DHCSR).

Overview of Cycle Mode

In Cycle Mode, after each processor clock cycle the core collects a snapshot of the processor’s current state. This snapshot includes contents of core registers like the program counter, stack pointer, and general purpose registers. The snapshot is sent off-chip via the Embedded Trace Macrocell (ETM), allowing an external debug probe to reconstruct the processor’s execution flow. Meanwhile, the processor continues executing instructions uninterrupted.

Cycle Mode provides instruction trace with minimal intrusion, unlike breakpoint-based debugging which halts execution on each breakpoint hit. This allows real-time debugging of timing-sensitive code sections that would otherwise be difficult when halted. Cycle Mode also enables profiling tools to collect detailed execution statistics for performance optimization.

Enabling Cycle Mode on Cortex-M0

To enable Cycle Mode debugging on a Cortex-M0 processor, the following steps must be taken:

1. Configure the ETM interface – The ETM must be set up to receive trace data from the core. This involves setting up the ETM trigger registers, config registers, and other ETM-specific settings.
2. Enable trace pins in IO configuration – The ARM CoreSight trace pins like ETMTRACECLK, ETMTRACEDATA[x] need to be enabled in the processor’s IO configuration.
3. Set DEMCR.TRCENA – The DWT (Data Watchpoint and Trace) module’s Trace Enable bit must be set to 1 to enable tracing.
4. Set DHCSR.C_DEBUGEN – The debugger must enable debug mode by setting this bit to 1.
5. Set DHCSR.C_HALT – Halt the core by setting this bit to 1.
6. Set DHCSR.C_DSM – To enable Cycle Mode, the Debug Single Mode bit must be set to 1.
7. Clear DHCSR.C_HALT – Finally, clear the Halt bit to 0 to start tracing.

The processor will now enter Cycle Mode and begin streaming trace data off-chip that can be decoded and analyzed. The DHCSR register bits can be accessed using the debugger or test interface.

Configuring Cycle Mode Behavior

There are a few Cycle Mode settings that can be configured to control the tracing behavior:

• Sample rate – The ETM tracing can be set up to trace every cycle or at some decimated rate to reduce trace bandwidth.
• State matching – State matching allows tracing to only happen when certain conditions are met, like specific PC value or register contents.
• Trigger position – Determines if a trigger event causes a trace before or after the event.
• Trace start/stop – Tracing can be programmed to start and stop on specified conditions using ETM triggers.

By carefully configuring these settings, Cycle Mode can be optimized to trace only the desired sections of code to minimize trace data volume.

Retrieving Trace Data

The trace data gets output over a parallel trace port or high-speed serial trace port. An external trace probe is required to capture the trace data. Popular probes include:

• Segger J-Link Probes
• ULINK2 – Provides high-speed bridging to USB
• Xilinx ChipScope Probes

The trace data can then be reconstructed and analyzed using tools like:

• Segger Ozone – Converts trace to disassembly view with statistics
• ARM DS-5 – Integrates trace with debug IDE
• Percepio Tracealyzer – Focus on visualization and timing analysis

These tools integrate the raw trace data with symbol information to produce meaningful views of program execution flow, timing, and profiling statistics.

Cycle Mode Limitations

While Cycle Mode is a powerful tool, there are some limitations to be aware of:

• Higher bandwidth requirements compared to lighter trace modes
• Limited execution history due to trace buffer size
• No data trace – only instruction addresses are traced
• Complex triggering capabilities not available in Cortex-M0
• Debug power consumption increases due to tracing

Cycle Mode trades off some amount of intrusion and complexity for comprehensive instruction trace. Other trace modes like Branch Trace may be more suitable for power-sensitive embedded applications.

Using Cycle Mode for Debugging

Here are some examples of how Cycle Mode can be leveraged for debugging:

• Interrupt issues – Trace can detect excess latency and recursion
• Task scheduling – Validate RTOS task timing and preemption
• Boot problems – Identify bugs early in the boot process
• Memory errors – Detect bad pointer accesses and corruption
• Performance optimization – Find hot code paths and cache issues

The ability to see a complete profile of code execution without halting the system enables many advanced debugging techniques.

Conclusion

Enabling Cycle Mode on Cortex-M0 requires configuring the ETM interface, setting debugger register bits, and connecting a trace probe. Careful configuration allows optimizing the trace behavior. Retrieved trace data can be visualized and analyzed using commercial tools. Cycle Mode provides powerful real-time debugging and profiling capabilities despite limitations like trace buffer size. With an understanding of the tracing architecture and tools, developers can leverage Cycle Mode to debug even the most complex embedded systems.