Configuring the linker options correctly is crucial for building efficient and optimized applications for Cortex-M23 devices using uVision5. The linker is responsible for combining object files and libraries into the final executable. The linker options control memory layout, symbol resolution, regions for code and data, and more. Setting these options incorrectly can result in a non-functioning or bloated application binary.
Understanding Cortex-M23 Memory Architecture
The Cortex-M23 processor has a Von Neumann architecture with unified address space for code and data. It has separate flash and SRAM memories connected over the AMBA 3 AHB-Lite bus. The on-chip flash is used for storing code and read-only data while SRAM stores writable data. The processor also has tightly coupled memory for high-performance access.
The linker needs to be configured to place code and read-only data in flash and writable data in SRAM. It also needs to take advantage of the tightly coupled memory for time-critical code and data. Keeping these architectural details in mind will help set up the linker optimally.
Essential Linker Settings
Specify Target Processor
The first step is to set the target processor to Cortex-M23 in the device manager. This will pre-configure some of the linker settings like memory regions and processor defines. Double check that the device variant matches the exact M23 chip being used.
Set Memory Regions
The linker needs to be told where to place code and data in the target memory map. The MEMORY section defines the start address, length, and attributes of each memory region. Flash and SRAM regions must be defined along with any tightly coupled memory. The attributes specify if the region is for code or data.
Configure Memory Placement
The linker now needs to know what content to place in which memory region. The SECTIONS directive controls this. Code and read-only data must go in flash while writable data goes in SRAM. Any performance-critical functions should be placed in tightly coupled memory.
Specify Stack and Heap
The stack and heap memory allocations need to be defined. The stack takes up memory from high addresses growing down while the heap grows up from lower addresses. Sufficient SRAM must be left for both based on application requirements. The heap can be omitted if dynamic allocation is not used.
Advanced Optimization Options
Split Code and Data
Splitting code and data into separate sections allows the linker to place them optimally. Function pointers also benefit since data sections can be relocated independently while code remains static.
Garbage Collection
Dead code removal or garbage collection strips unused code and data from the final binary. This minimizes application size at virtually no cost. Garbage collection should always be enabled.
Interwork Calls
This enables calls between ARM and Thumb code without overhead. Cortex-M23 only supports Thumb so this option is not needed.
Tail Calls
The compiler can optimize stack usage by converting tail call sequences to jumps. This also needs function and data sections split. Useful for stack-constrained designs.
Linker File Templates
uVision provides pre-configured linker files for each processor and toolchain. These contain all the necessary sections and options. They serve as a good starting point for customization. Verify the memory regions match the target device. Tweak placements and sizes as needed.
Linker Validation
Correct linker configuration must be validated before deployment. Memory use should be analyzed to catch overflows or fragmentation. Unused memory can be reduced. Code placement should be verified especially in tightly coupled memory. Fail to validate the linker settings and the application may not work as intended.
Conclusion
Configuring the linker properly is key to an efficient Cortex-M23 application with uVision5. The target processor and memory architecture guide what linker options are needed. Sections place code and data into the correct memories. Advanced optimizations reduce size and improve performance. Pre-configured templates provide robust default settings. Be sure to validate the memory use matches expectations after configuring the linker.
