The Cortex-M55 is the latest microcontroller from ARM designed for advanced artificial intelligence and machine learning applications. It has several memory configuration options that allow system designers to optimize memory usage for their specific needs.
On-Chip SRAM
The Cortex-M55 includes up to 2MB of on-chip SRAM directly available for code and data storage. This provides fast access memory for time-critical operations and temporary data storage without needing to access slower external memory. The specific amount of SRAM can be selected based on the application requirements.
Private SRAM
Up to 256KB of the SRAM can be configured as private SRAM accessible only by the Cortex-M55 core and not shared with other bus masters. This is useful for storing private stack and cache data.
Shared SRAM
The remaining SRAM is shared SRAM accessible by the Cortex-M55 core and other bus masters via the system bus. This provides general purpose storage for code and data.
External Memory Interfaces
In addition to internal SRAM, the Cortex-M55 includes interfaces to connect to external memories. This allows much larger memory capacities to be accessed when needed.
LCD-TFT Interface
The LCD-TFT interface provides up to 32MB of memory mapped access to an external graphics random access memory (GRAM). This allows storage of graphical data framesbuffer data.
QuadSPI Interface
The QuadSPI interface supports connecting external flash memory devices. It can support up to 4 parallel read/write lines to provide high bandwidth access to execute code directly from external flash.
OctalSPI Interface
For even higher bandwidth, the OctalSPI interface can support up to 8 parallel read/write lines to very fast external flash devices. This allows executing code directly with minimal latency.
DDR Interface
A DDR interface is provided to connect external DDR memory. This provides a balance of high density off-chip memory with reasonable access latency. Up to 1GB of external DDR is supported.
Memory Protection Unit
The Cortex-M55 includes a memory protection unit that allows controlling access permissions for on-chip and external memory regions. This allows protecting sensitive data from unauthorized access.
MPU Regions
Up to 16 MPU regions can be defined with configurable base address, size, access permissions, and memory attributes. Each region can be enabled/disabled independently.
Access Permissions
Read, write, and execute permissions can be configured per region per bus master. This allows precisely controlling which bus masters can access which memory regions.
Memory Attributes
Attributes like cacheable, bufferable, shareable can be configured per region to control memory access behavior. Cache can be disabled for memory regions as needed.
Instruction and Data Caches
The Cortex-M55 includes level 1 instruction and data caches to improve performance when accessing external memories. This helps reduce latency and increase throughput.
Instruction Cache
Up to 64KB 4-way set associative instruction cache is provided. It helps reduce instruction fetch latency and improves performance executing code from external memory.
Data Cache
Up to 64KB 4-way set associative data cache is also provided. This helps reduce data access latency and improve throughput for data accesses to external memory.
Cache Coherency
The caches support cache coherency with other bus masters. This ensures data consistency between processors and caches in multi-core systems.
Tightly Coupled Memory
The Cortex-M55 supports up to 16MB of dedicated tightly coupled memory (TCM) to provide low latency access without contention. The TCM acts as level 0 instruction and data memories.
Instruction TCM
Up to 8MB instruction TCM provides low latency instruction fetch similar to cache but without contention. Critical code can be placed here.
Data TCM
Up to 8MB data TCM provides single cycle access latency for data. Frequently accessed data can be placed here.
Software Management
The TCM is managed in software, giving full flexibility over usage. TCM allocation can be changed dynamically based on application behavior.
Memory Access Speeds
The different memory types provide a range of access speeds and latencies:
- SRAM – 1 cycle access
- TCM – 1 cycle access
- Instruction Cache – 2 cycles minimum
- Data Cache – 2 cycles minimum
- QuadSPI – 4 cycles minimum
- OctalSPI – 2 cycles minimum
- DDR – 10+ cycles typically
So in summary, the Cortex-M55 supports a flexible mix of fast on-chip SRAM and TCM with sizes up to megabytes, along with external flash and high density memories up to gigabytes, enabling system designers to optimize memory usage for their application requirements.
Example Memory Configurations
Here are some examples of how memory could be configured for different types of Cortex-M55 applications:
Low Power IoT Endpoint
- 256KB SRAM
- 1MB external QuadSPI flash
Minimizes on-chip memory for a low cost and low power optimized implementation. External flash provides code and data storage.
Advanced Driver Assistance System
- 1MB SRAM
- 16MB TCM
- 64MB external DDR
Uses maximum on-chip SRAM and TCM for performance critical tasks like sensor fusion and tracking algorithms. External DDR provides storage for deep neural networks and image data.
Autonomous Robot
- 512KB SRAM
- 8MB instruction TCM
- 8MB data TCM
- 1GB external DDR
TCM provides low latency memory for real-time control tasks. DDR provides capacity for large neural networks, maps, and other data.
Conclusion
In summary, the Cortex-M55 provides a lot of flexibility when it comes to memory configuration. Key options include:
- Up to 2MB on-chip SRAM
- Up to 16MB TCM
- External flash support via QuadSPI and OctalSPI
- External DDR support up to 1GB
- Configurable memory protection
- Instruction and data caching
This allows system designers to optimize memory usage for the particular performance, power, and cost requirements of their AI and ML applications built around the Cortex-M55 processor.
