Cortex-M0+ microcontrollers (MCUs) from ARM offer a good balance of performance, power efficiency, and cost for a wide range of embedded applications. While there are some common features across Cortex-M0+ chips, there can also be significant differences between models from different manufacturers. Overall, Cortex-M0+ strikes a compromise between customization and generalization.
Common Features of Cortex-M0+ MCUs
As a 32-bit ARM processor optimized for embedded applications, all Cortex-M0+ MCUs have some standard capabilities:
- 32-bit ARM Cortex-M0+ core running at up to 50 MHz
- Thumb-2 instruction set for improved code density
- Nested Vectored Interrupt Controller (NVIC) for managing interrupts
- SysTick timer for basic task scheduling
- Standardized debug and trace interfaces
- Power management features like sleep and deep sleep modes
- Memory protection unit for security
The Cortex-M0+ architecture is highly configurable by design. ARM offers the processor IP along with documentation and integration tools for chipmakers to customize and implement in their own manufacturing process. This allows the Cortex-M0+ CPU to be targeted to a wide range of end applications with the integration of various peripherals and I/O interfaces.
Differences Between Vendors
While the processor core itself is standardized by ARM, the surrounding components will vary between vendors. Here are some of the main ways Cortex-M0+ MCUs can differ:
- Manufacturing process – Chip fabrication process affects power, performance, and cost. Common nodes are 40nm, 28nm, and 22nm.
- Clock speed – Ranges from 24 MHz to 50 MHz. Higher is faster but uses more power.
- Flash memory – On-chip non-volatile storage from 16 KB up to 256 KB typically.
- SRAM – On-chip memory for data, code, and stacks. Varies from 4 KB to 64 KB.
- Peripherals – UARTs, SPI, I2C, CAN, USB, ADCs, DACs, timers, PWM, etc. Support for different interfaces.
- Packages – Available in different physical packages like QFP, BGA, QFN, etc. for integration.
- Software tools – Coding, debugging, and flash programming tools will differ between vendors.
While there is a diverse set of Cortex-M0+ devices, certain combinations of features tend to be more common for targeting particular applications. Low power designs might have slower clocks, smaller memories, and more analog integration. Cost-sensitive designs may use older process nodes and smaller packages. More advanced applications support faster clocks, more peripherals, and hardware security features.
Generalization for Broad Use
The benefit of the unified Cortex-M0+ architecture is that software and tools can be reused across different microcontrollers. Code written for one Cortex-M0+ device can usually be adapted to run on another with modest modification. Debugging probes and IDEs support the standard ARM CoreSight debug specification. RTOS and middleware commonly support Cortex-M0+ as one of the target architectures. This improves software reuse and reduces development costs.
Reference designs and application notes for Cortex-M0+ provide a starting point for many projects. Rather than starting from scratch, significant hardware and firmware code can be reused when choosing a Cortex-M0+ microcontroller. TheARM ecosystem around the Cortex-M0+ is extensive and allows faster time-to-market.
For less demanding applications that only require basic I/O, timers, UARTs, etc. almost any Cortex-M0+ microcontroller will suffice. The core ARM architecture provides enough processing performance and capability for simple control and sensing applications. Variations in memory, clocks speeds, and peripherals matter less.
Customization for Specific Use Cases
For applications with tougher performance requirements, more advanced interfaces, or stringent power budgets, the differences between Cortex-M0+ devices become more significant. The ideal microcontroller for one application may be completely unsuitable for another. Some examples requiring customization:
- Sensor hub processing sensor fusion algorithms requires fast clock and math co-processor.
- Motor control needs many PWM outputs and fast ADC sampling.
- Voice recognition needs hardware digital signal processing.
- Battery-powered designs need lowest possible energy usage.
The wide variety of Cortex-M0+ microcontrollers allows tailoring to the specific use case requirements. One design may emphasize analog and have multiple ADCs and comparators. Another design may focus on connectivity with USB, Ethernet, and wireless radios. The flexibility of the Cortex-M0+ ecosystem allows chip vendors to create customized solutions.
Example Vendor Customizations
Here are some examples of how major vendors have customized Cortex-M0+ MCUs for different applications:
ST Microelectronics STM32L0 Series
- Focus on ultra-low power for IoT edge nodes.
- Uses a 28nm FD-SOI process for efficient power scaling.
- Has multiple low power modes for sleep current down to 0.6 μA.
- 2 UARTs, 2 SPI, I2C, USB for connectivity.
NXP LPC800 Series
- Cost-optimized family for simple control applications.
- Uses 40nm process for low cost.
- Up to 50 MHz clock speed.
- GPIO, USART, SPI, I2C, and timers.
- Available in compact WLCSP packages.
Microchip SAM L10/L11 Series
- Focus on hardware security features.
- Integrated crypto authentication and secure boot.
- Supports mTouch capacitive touch sensing.
- Multiple serial interfaces and ADCs.
- Targets security-critical IoT edge nodes.
Conclusion
The Cortex-M0+ architecture strikes a balance by providing a standardized processor platform that enables software reuse, while still allowing customization by vendors for differentiation. For generic applications, the core ARM CPU provides good performance per MHz and can be leveraged across different microcontroller families. But for more advanced embedded systems, choosing a Cortex-M0+ MCU tailored for the specific use case requirements is crucial.
