Adding JTAG/SWD debug capability to a Cortex-M0 microcontroller can sometimes be tricky and fail unexpectedly. This is often due to subtle differences between MCU models as well as complexities in properly configuring the debug interface. With some diligence and methodical troubleshooting, the root cause can usually be identified and resolved.
Common Reasons JTAG/SWD Fails on Cortex-M0
Incorrect JTAG/SWD Pin Connections
The first thing to check is that the JTAG/SWD pins on the MCU are properly connected to the debug probe. The pinout and layout for these signals can vary between MCU models so consulting the datasheet is essential. Some common issues are mismatched pin assignments, failure to tie pull-up/pull-down resistors, or lack of connectivity due to broken PCB traces.
Invalid or Missing JTAG/SWD Configuration
The Cortex-M0 debug module requires correct initialization and configuration via the Debug Access Port (DAP). This includes enabling debug mode, configuring the DAP, and selecting the appropriate debug interface (JTAG vs SWD). Debug probes have onboard ROM which handles this initialization, but it must be compatible with the specific MCU model.
Security Locks or Memory Protection
Many Cortex-M0 MCUs include security features like flash lock bits or memory protection units. If these are not properly handled, they can override debug access even if the interface is working physically. Make sure to unlock debug and avoid setting protections on memory regions needed for debugging.
Faulty External Debug Hardware
Issues with the debug probe itself, its drivers, or the USB connection to the host computer can manifest as JTAG/SWD failures. Try a known-good probe on the target to rule this out. Loose probe connections, poor probe power regulation, and buggy probe firmware can all prevent proper debug access.
Noise or Signal Integrity Issues
Electrical noise coupled onto the JTAG/SWD lines or trace impedances that distort the signals can cause intermittent glitches or total failure. Careful PCB layout, adequate decoupling, and bypass capacitors on the target system can help mitigate these issues.
Step-by-Step Debugging Process for Cortex-M0 JTAG/SWD
1. Verify Debug Module is Enabled
Consult the MCU datasheet and reference manual to locate the debug enable bit in the Debug Access Port (DAP). This bit controls whether the debug module communicates over the JTAG/SWD pins. Make sure it is set to 1 to enable debug access.
2. Check JTAG/SWD Pin Connections
Use a multimeter to test connectivity between MCU pins and debug probe. Verify 5V, GND, SWDIO, and SWCLK (plus /TRST if using JTAG) are properly wired based on your schematic and pinout diagram.
3. Initialize DAP and Debug Interface
Verify the debug probe is properly initializing the DAP port on your MCU. This requires a ROM table compatible with the chip. You may need to select different firmware or upgrade the probe.
4. Confirm No Security Locks are Enabled
Check for any flash security lock bits or MPU settings that could block debug access. Make sure to unlock the chip and avoid memory protection on regions like flash, SRAM, and debug module registers.
5. Test with Known-Good Probe and Target
Try substituting a proven debug probe and simple test board to identify any issues with target system or existing probe hardware/firmware.
6. Check Target Power Supplies and Decoupling
Inspect power supply voltages under operation and measure ripple. Add filtering capacitors if noise is excessive. The debug interface is sensitive to power issues.
7. Analyze JTAG/SWD Physical Signals
Use an oscilloscope or logic analyzer to verify JTAG/SWD connections are clean, without distortion or reflections. Add series resistors if necessary to dampen reflections.
8. Modify PCB Traces for Signal Integrity
Tune trace width and spacing to achieve proper 90Ω differential impedance for SWDIO/SWCLK. Minimize stubs, vias, and length mismatches. Route signals away from noise sources.
9. Update MCU or Debug Probe Firmware
Check chip and probe vendor websites for firmware patches that address any silicon bugs or debug initialization issues impacting your hardware version.
10. Consult Manufacturer Application Notes
Chip vendors often release detailed application notes on optimally configuring debug. Also check errata for your MCU revision.
Bypassing JTAG/SWD for Alternate Debug Methods
Embedded Trace Macrocell (ETM)
Some Cortex-M0 MCUs integrate an ETM module for instruction trace capture without needing SWD connectivity. This provides insight into code execution without halt-mode debugging.
Serial Wire Output (SWO)
The SWO pin can output debugging and instrumentation data from the Cortex-M0 real-time in normal operation. This provides trace visibility without halting execution.
Debug UART with Breakpoints
Instrumenting code with debug printouts over UART combined with software breakpoints can enable basic debugging without JTAG/SWD and with target running.
On-Chip Logic Analyzer
Some MCUs contain integrated logic analyzers to capture digital signals in real-time without debug probes. This is helpful for monitoring peripherals and I/O.
In-Circuit Emulators (ICE)
Full in-circuit emulators act as drop-in target replacements for more sophisticated and transparent debugging compared to JTAG/SWD probes.
Conclusion
While troubleshooting JTAG/SWD connectivity on Cortex-M0 can be frustrating, methodically verifying key debug requirements and addressing common issues will ultimately allow successful access. For non-critical debugging, alternate techniques like debug UART output or on-chip trace tools may suffice. With the right approach, most JTAG/SWD problems can be resolved and full unobtrusive debug achieved.
