The ARM Cortex-M0 and Cortex-M0+ are two of ARM’s most popular low power microcontroller cores. Both are 32-bit RISC processors designed for embedded applications requiring high efficiency and low cost. The Cortex-M0+ is an evolution of the Cortex-M0 with improvements in performance, power consumption and features.
Key Differences
Here are some of the main differences between the Cortex-M0 and Cortex-M0+:
- The Cortex-M0+ has higher performance with a faster CPU clock frequency of up to 50 MHz versus 24 MHz for the M0.
- The M0+ includes architectural optimizations that reduce execution cycles for common instructions.
- The M0+ introduces dual-issue instructions that can execute some operations in parallel.
- The M0+ has lower power consumption thanks to advanced sleep modes and logic optimizations.
- The M0+ includes bit manipulation instructions for faster bitfield operations.
- The M0+ supports the Micro Trace Buffer (MTB) for improved real-time debugging.
- The M0+ core adds optional memory protection unit (MPU) support for improved software robustness.
- The M0+ implements the ARMv6-M architecture while the M0 uses the ARMv6-M baseline.
CPU Core Architecture
Both the Cortex-M0 and M0+ implement a stripped down version of the ARMv6 instruction set optimized for low-cost embedded applications. Key features of the CPU core architecture include:
- 3 stage pipeline (Fetch, Decode, Execute)
- 32-bit RISC architecture with 16-bit Thumb instruction set
- Up to 24 MHz max clock frequency for M0, 50 MHz for M0+
- Fixed 4 cycle execution time for most Thumb instructions
- Hardware multiply and divide instructions
- Optional MPU with 8 regions and configurable bus access permissions
- Built-in debug module supporting breakpoints, watchpoints, profiling, etc.
- Extensive interrupt support with nested vectored interrupt controller
- Wakeup Interrupt Controller (WIC) for managing interrupts during low power mode
The M0+ improves upon the M0 architecture with dual-issue instructions, bit manipulation extensions, MTB tracing, and overall optimizations to increase performance and reduce power consumption. But both cores share the same fundamental 3 stage pipeline and RISC Thumb instruction set for flexibility across a wide range of ultra low power applications.
Memory Subsystems
The Cortex-M0 and M0+ integrate tightly coupled memory subsystems to optimize performance and energy efficiency. Key memory features include:
- Support for single cycle access Tightly Coupled Memory (TCM) for instructions and data
- Up to 4 configurable TCM interfaces with up to 64KB each for instructions and data
- Embedded Flash controller for code execution from flash memory
- Bus interfaces supporting AHB-Lite, APB, advanced high performance bus (AHB)
- Bit-banding for single-cycle bit access of memory words
- Optional MPU to enforce memory access permissions
Making use of TCM memory blocks for time critical code and data gives a significant performance boost compared to external memory access. The M0+ allows overlapping access to both TCM ports, enabling more parallel memory activity.
Low Power Operation
As small microcontrollers meant for energy constrained devices, both the Cortex-M0 and M0+ implement extensive power saving features:
- Support for multi-stage low power sleep modes
- Wakeup Interrupt Controller (WIC) to handle interrupts in sleep/deep sleep modes
- Logic gating to power off unused modules
- Register retention in low power modes to avoid reinitialization
- Integrated power profiles for quick enablement of power features
- Dynamic voltage scaling and independent clock gating for flexible power schemes
The M0+ provides even lower power consumption through additional automatic power optimizations in the processor pipeline and logic blocks. For minimal power usage, the Cortex-M0/M0+ cores can be configured to operate down to just a several microamps of current draw in the deepest sleep modes.
Development Tools
ARM provides a full ecosystem of development tools for the Cortex-M0/M0+ including:
- Cortex Microcontroller Software Interface Standard (CMSIS) software framework
- Compiler support (GCC, ARM, IAR)
- Debuggers and IDEs with driver libraries
- RTOS board support packages
- CODEO code analyzer for optimization
- mbed development platform to speed up prototyping
The simple architecture of the M0/M0+ enables support across a wide range of tools and RTOS platforms. CMSIS provides a common software framework to make development easier across multiple vendors. ARM’s large ecosystem also ensures toolchain support from multiple commercial and open source vendors.
Example Devices and Use Cases
The Cortex-M0 and M0+ target cost sensitive embedded applications requiring a balance of high performance and energy efficiency in a small footprint. Example devices and use cases include:
- Wearables and internet of things sensors
- Industrial control and monitoring
- Low power wireless products (Bluetooth, WiFi)
- Home automation and smart home devices
- Medical devices and equipment
- Motor control and power conversion
- Camera modules and surveillance systems
Leading silicon vendors such as NXP, STMicroelectronics, Microchip, Cypress, Renesas, Toshiba and others offer Cortex-M0/M0+ based microcontrollers suitable for a wide range of embedded applications. The M0 cores strike a balance of performance, power, size and cost that makes them popular choices for low complexity control tasks in energy sensitive devices.
Summary and Conclusion
The ARM Cortex-M0 and Cortex-M0+ deliver efficient, RISC-based 32-bit performance in a tiny memory footprint suitable for small embedded systems. The M0+ builds on the success of the popular M0 improving performance, power consumption, and adding features like bit manipulation, memory protection, and advanced debugging capabilities. Both offer impressive performance per MHz, fast interrupt handling, and extensive power saving modes. The Cortex-M0/M0+ have become standard choices for low power embedded designs across consumer, industrial and medical applications.
