The Cortex-M0 processor from ARM is designed to provide an ultra low power 32-bit CPU solution for microcontroller and deeply embedded applications. The processor is optimized to deliver the best power vs performance ratio, making it ideal for power-constrained devices that need to balance processing capabilities with extended battery life.
Low Power Design Philosophy
The Cortex-M0 employs a variety of techniques and optimizations at the architecture, logic, circuit, and physical implementation levels to reduce power consumption. The key tenets of the low power design approach are:
- Minimizing switching activity through an efficient pipeline, static design techniques, and extensive clock gating.
- Operating the pipeline at lower voltages when possible to reduce dynamic power.
- Integrating power control throughout the design to enable independent power management of each core component.
- Optimizing transistor sizes to reduce leakage current while maintaining performance.
- Providing multiple low power modes to selectively power down logic and memory.
By leveraging these techniques, the Cortex-M0 delivers the highest energy efficiency in its class of embedded processors. Power consumption can scale dynamically based on application requirements.
Low Power Modes
The Cortex-M0 supports multiple low power modes that allow parts of the system to be selectively powered down when not needed. This saves energy and extends battery life in duty-cycled systems that have idle periods between active processing times.
Sleep Mode
Sleep mode powers down the CPU, most peripherals, and SRAM. The core can be woken up by an interrupt when needed. This provides significant power savings while still retaining some state and data in memory. The fast wake up time allows quick response to events.
Deep Sleep Mode
Deep sleep powers down more of the system including all SRAM. Only basic peripherals like the watchdog timer remain active. This provides the lowest power state aside from OFF mode. The wake up time is longer as context needs to be restored.
Off Mode
This mode completely powers down the entire Cortex-M0 system. No code executes and all state in registers and SRAM is lost. The system is restarted similar to a cold reset when power is applied again. Off mode gives the lowest power but is not useful when SRAM data contents need to be maintained.
Dynamic Voltage Scaling
The Cortex-M0 supports multiple operating voltages from 1.65V down to 0.9V. Lower voltages drastically reduce dynamic switching power. The operating voltage can be scaled dynamically based on the performance needs at a given time.
When full processing speed is needed, the CPU can run at higher voltages. For low throughput standby modes, the voltage can be reduced to save power. The voltage only needs to be high enough to support the currently required clock frequency.
Integrated Power Control
Fine-grained power control is integrated throughout the design of the Cortex-M0. Power domain gates allow independent control of power for each part of the system such as the CPU core, bus interfaces, and peripherals. Unused sections can be powered down to minimize wasted power.
In addition, extensive use of clock gating is employed to prevent clock signals from toggling when a component is idle. This eliminates unnecessary switching activity which helps reduce dynamic power.
Architectural Optimizations
At the architecture level, the Cortex-M0 employs an efficient 3-stage pipeline to minimize switching activity. Pipelining allows operations to be overlapped for better performance, but deeper pipelines tend to increase power consumption.
The short pipeline in Cortex-M0 provides a good balance of performance while reducing unnecessary logic switching. Branch prediction is also used to minimize pipeline stalls, further improving energy efficiency.
Logic Optimizations
Transistor sizes throughout the design are optimized to balance switching speed versus leakage current. Larger transistors switch faster but also leak more power when idle. Minimum transistor sizes are used in non-critical paths to reduce leakage while meeting overall performance targets.
Low power design techniques like multi-threshold voltage logic, multi-Vt libraries, and special cell design are leveraged. Multi-threshold techniques use both high and low threshold transistors on the same die to optimize for speed or low leakage where needed.
Physical Implementation
At the physical level, low power best practices are applied such as:
- Careful floorplanning and placement to minimize wire lengths and capacitive loads.
- Extensive use of power/ground strapping and mesh structures to avoid voltage drops.
- Leveraging multiple transistor threshold voltage libraries.
- Employing multi-voltage designs with both core and I/O supply voltages.
- Using low-K dielectrics and copper interconnect for reduced capacitance and resistance.
Together, these physical implementation techniques minimize power supply noise while reducing parasitic capacitance and resistance to conserve dynamic and static power.
Configurable Low Power Options
The Cortex-M0 offers extensive configurable options to tune power vs performance for each application:
- Voltage Range: Support for voltages from 1.65V down to 0.9V.
- Frequency Range: CPU clock speeds from 0 MHz up to 50 MHz.
- Wake Up Time: Can be configured based on selected low power modes.
- Peripheral Clocks: Each peripheral clock can be gated off when idle.
- Memory Gates: SRAM power gates can be controlled for unused memory regions.
Architectural options are also provided to disable certain CPU features to save power:
- MPU: The Memory Protection Unit clock can be gated to conserve power.
- Bus Matrix: The bus interconnect provides flexibility but can be disabled for simpler single bus systems.
- FPU: Disable floating point unit to save power in integer-only applications.
By tuning these options for a specific OS, workload, and performance targets, the Cortex-M0 can be optimized to deliver the desired balance of low power and performance.
Benchmark Performance and Power
For a typical 90nm low power process, the Cortex-M0 can deliver:
- Frequency range from 24 MHz to 50 MHz at 1.2V.
- As low as 8.3 CoreMark/MHz.
- Power consumption of 1.14 mW/MHz at 1.2V (simulated).
- Idle current of 34 μA/MHz (simulated).
This level of power efficiency provides excellent performance per watt compared to other microcontroller architectures. The ability to dynamically scale voltage and frequency based on workload provides further optimization for low power applications.
Use Cases and Applications
The Cortex-M0 is designed to bring ARM’s low power architecture advantages to ultra compact, resource constrained devices. Example applications include:
- Sensor Nodes: Battery powered sensors for industrial, consumer, or infrastructure monitoring.
- Wearables: Activity trackers, smart watches, medical monitors.
- IoT End Nodes: Low power wireless nodes in mesh networks.
- Smart Home: Low cost home automation devices and sensors.
- Appliances: Microcontrollers for low power white goods and appliances.
The Cortex-M0 enables these types of products to have greater intelligence, connectivity, and battery life in small form factors. More advanced but lower power processing opens up new possibilities for embedded products.
Software and Development Tools
The Cortex-M0 processor is supported by ARM’s ecosystem of tools and software:
- Compilers: The ARM Compiler 6 toolchain offers full C/C++ support for building and optimizing software to run on Cortex-M0.
- IDEs: Mainstream IDEs such as Keil MDK, IAR EWARM, and ARM Development Studio 5 support Cortex-M0 application development.
- RTOS: FreeRTOS and other real-time operating systems can be used.
- Debuggers: ULINKpro, ULINKplus, and ULINK2 debug probes enable download, flash programming, and JTAG debug.
The wide range of proven development tools enables software engineers to be highly productive building applications on Cortex-M0 based microcontroller designs.
Optimizing Software for Low Power
To fully realize the benefits of the low power hardware architecture, software needs to be optimized along similar principles:
- Minimize activity: Reduce unnecessary computation and I/O to limit power draw when idle.
- Use low power peripherals: Favor low power peripherals like Real Time Clock over CPU intensive software loops.
- Minimize memory accesses: Access memory judiciously and optimize code for cache hits.
- Suspend processing: Use sleep modes with fast wake up times to shutdown between events.
- Throttle speed: Operate CPU at lower speeds when performance allows.
With aligned hardware architecture and software techniques, the Cortex-M0 enables revolutionary low power applications to be built.
Conclusion
The Cortex-M0 microcontroller CPU provides an optimized combination of low power features across architecture, logic design, circuit techniques, and physical implementation. Configurable options allow voltage, speed, and component power gates to be tuned for each application. When paired with low power software approaches, the Cortex-M0 enables a new generation of power efficient embedded devices with advanced capabilities.
From deeply embedded sensor nodes to consumer wearables and IoT endpoints, the Cortex-M0 strikes an ideal balance of ultra low power with enough performance for intelligent local processing. Its efficiency even enables battery-powered applications to incorporate more advanced algorithms for machine learning and analytics. As one of ARM’s most power optimized architectures, Cortex-M0 will open up exciting new possibilities in the world of deeply embedded low power devices.
