Cortex M0+, AHB state during Exception

The Cortex-M0+ processor from Arm is an ultra low power 32-bit RISC CPU core designed for microcontroller applications. It builds on the success of the earlier Cortex-M0 core by adding new features like dual-issue pipeline, configurable memory protection unit, and higher energy efficiency while maintaining full code compatibility with Cortex-M0.

One key aspect of Cortex-M0+ operation is how it handles exceptions and interrupts. When an exception or interrupt occurs, the processor must switch from normal program execution to exception handling seamlessly. This requires coordination between the processor core and the peripherals connected via the AMBA AHB bus interface.

AHB Bus Interface

The Cortex-M0+ integrates an AMBA AHB-Lite bus interface to connect to memory and peripherals. AHB-Lite is a simplified version of the AHB protocol optimized for on-chip communication in microcontrollers. It has features like:

• Single master – Only Cortex-M0+ acts as AHB master
• Pipelined operation for higher throughput
• Burst transfers for improved bus efficiency
• Simplified handshake mechanism compared to full AHB

The AHB bus consists of the HCLK clock line, HRESETn reset line, HADDR address bus, HTRANS transfer type bus, HWRITE read/write indicator, HSIZE transfer size bus, HBURST burst transfer configuration bus, and the HWDATA write data bus.

AHB States

The AHB bus interface of Cortex-M0+ can be in one of the following states:

• IDLE – No transfers are currently happening over the AHB bus.
• BUSY – A transfer is currently in progress.
• NON-SEQUENTIAL – A non-sequential transfer like single access or 4-beat wrap burst is in progress.
• SEQUENTIAL – A sequential transfer like an unspecified length burst is in progress.
• RETRY – The current bus transfer failed and will be retried.
• SPLIT – A split transfer is in progress.

The Cortex-M0+ AHB interface state machine controls the transitions between these states based on the transfer type and handshake signals from the slave peripherals.

AHB State during Exceptions

When the Cortex-M0+ processor takes an exception or interrupt, it has to save context, change stack pointer, and start executing the exception handler. This transition must also coordinate with the AHB bus interface state machine.

The exact AHB state sequence during an exception depends on the state before the exception –

Exception from IDLE State

1. Core signals the bus interface to move from IDLE to BUSY state
2. Bus interface sends out the vector read request for exception handler
3. After vector read completes, bus returns to IDLE
4. Core executes exception handler routine

Exception during BUSY State

1. Core signals exception to the bus interface
2. Bus interface completes current transfer
3. Bus interface moves from BUSY to IDLE
4. Same sequence as exception from IDLE state follows

Exception during SEQ State

1. Core signals exception to the bus interface
2. Bus interface interrupts the sequential burst
3. Bus interface moves from SEQ to BUSY
4. Same sequence as exception from BUSY follows

Exception during NONSEQ State

1. Core signals exception to the bus interface
2. Bus interface completes the current non-sequential transfer
3. Bus interface moves from NONSEQ to BUSY
4. Same sequence as exception from BUSY follows

So in summary, on exception the bus interface completes any ongoing transfer, moves to BUSY state, performs the vector read for the handler, then finally moves back to IDLE state for handler execution.

Arbiter and Timeout Control

To prevent bus hangs during exceptions, the Cortex-M0+ AHB interface has a bus arbiter and timeout control logic.

The arbiter ensures fair access to the bus for all masters. Though Cortex-M0+ is the only master, in multi-core scenarios the arbiter facilitates inter-core hand-overs.

The timeout control logic triggers timeouts if any non-sequential transfer takes too long to complete. This prevents deadlocks due to faulty slaves. On timeout, the transfer is cancelled and a bus error is signalled to the core.

Debug State Handling

When the Cortex-M0+ enters debug state, the AHB interface continues normal operation. Any ongoing AHB transfers are allowed to complete without interruption to prevent bus errors.

Once all outstanding transfers finish, the AHB state machine halts the start of any new off-chip transfers. However, the timer and watchdog peripherals can still initiate on-chip memory transfers during debug halt state for their normal operation.

The debug logic directly controls the HTRANS/HSEL lines when performing debug reads/writes over the AHB interface. All other AHB control signals continue to be driven by the bus interface state machine.

Upon exit from debug state, the AHB state machine seamlessly resumes normal operation – either staying in IDLE state or restarting a previously interrupted transfer.

Bus Fault Handling

Bus faults like illegal access, address errors, timeout errors etc. are signalled to the Cortex-M0+ core via the BusFault exception. The fault status information is captured in the Bus Fault Status Register (BFSR) and Bus Fault Address Register (BFAR).

Based on the BFSR, the BusFault exception handler can identify the source of the error and take appropriate action – whether to terminate execution or retry the failed transfer.

For faults during exception entry like vector read failures, the exception stacking ensures proper state recovery before signalling the BusFault.

Interaction with Other Components

The AHB interface state handling during exceptions is designed to work seamlessly with other components of the Cortex-M0+ system like:

• Nested Vectored Interrupt Controller (NVIC) – coordinating exception entry to not lose pending interrupts.
• SysTick Timer – handling timer ticks during exception processing.
• Memory Protection Unit (MPU) – programming region permissions to allow vector reads.
• Wake-up Interrupt Controller (WIC) – waking up the core from sleep/deep sleep state.

The extensive verification performed on the Cortex-M0+ design ensures glitch-free operation during normal and exceptional scenarios.

Configurable Options

To allow flexibility, some aspects of the Cortex-M0+ AHB interface are configurable:

• Idle time – configurable idle cycles before issuing bus request
• Write buffer depth – configurable master-side write buffer depth
• Maximum burst lengths for transfers
• Split transfer support

These options can be tuned to optimize bus performance for different applications. The arbiter and timeout control logic help maintain robustness across configurations.

Conclusion

In summary, the Cortex-M0+ AHB interface is designed to gracefully handle exceptions and interrupts. The bus state machine ensures that ongoing transfers complete without corruption while servicing exceptions with low latency. Timeout control prevents deadlocks and the AHB arbiter enables multi-master coherency.

Careful verification and integration with other components enable robust exception handling behavior. Configurable options provide flexibility to tune performance across different embedded applications. Overall, the Cortex-M0+ AHB interface enables building low power, high performance embedded systems with Arm.