Developing applications for ARM-based systems using Xilinx’s Vivado Design Suite on Windows can be challenging at times. Vivado provides a comprehensive integrated development environment (IDE) for synthesizing, implementing and debugging hardware designs, along with SDK for creating embedded software applications. However, users may encounter various issues when trying to get started with Vivado on Windows, especially if they are new to FPGA development.
In this article, we will explore some of the common Vivado problems faced by ARM developers on Windows platforms, along with potential solutions and workarounds.
License Activation Failures
Activating the Vivado license is one of the first steps after installation. However, the license manager may fail to activate the license due to firewall or antivirus software blocking access. Windows Defender or third-party antivirus programs could prevent the license manager from communicating with the Xilinx licensing server. Temporarily disabling firewalls and antivirus shields often resolves license activation problems.
If the evaluation license expires, users need to obtain a full production license. Xilinx provides node-locked, networked or floating licenses. License activation issues also arise when the wrong license is installed or license details do not match the current hardware configuration.
Long Installation Times
Depending on the system configuration, Vivado installation on Windows may take several hours to complete. The installer needs to extract a large number of files and components, which is resource intensive. Having an SSD instead of HDD, more RAM and multi-core processor speeds up the installation. Users may also disable antivirus scans during install to avoid any I/O bottlenecks.
For ARM users, the device support and ARM compilers significantly increase install time. If only FPGA development is needed, these options can be skipped to reduce installation duration. Monitoring resource usage helps identify any component causing delays.
GUI Crashes and Hangs
The Vivado IDE comprises multiple components interconnected using Tcl/Tk. At times, the GUI may crash or hang indefinitely due to issues with the OS, drivers or even insufficient resources. Updating Windows, graphics drivers and disabling CPU/RAM limits often improves stability. Switching between Edit and Apply may also help when GUI is non-responsive.
Vivado generates large reports for synthesis and implementation. Excessively long reports can overwhelm GUI and leads to sluggishness. Tweaking report strategies helps reduce this overhead. For critical crashes, Tech Support may request gdb logs to debug root cause.
Long Synthesis and Implementation Runtimes
Logic synthesis and place-and-route are extremely compute intensive. Larger FPGAs with complex designs may take hours to implement on Windows workstations. Multi-core processors, more RAM capacity and NVMe storage reduce runtimes. But Windows has higher OS overheads compared to Linux reducing overall performance.
Tuning synthesis and implementation options specifically for the target device also helps. Multi-threading computations using Tcl commands further improves speed by leveraging all CPU cores. Reducing optimization constraints enables the Vivado compiler to find solutions faster.
Intermittent Simulation Failures
The Vivado simulator combines various Verilog models and device primitives to functionally verify designs. At times, simulations may crash randomly or report unusable results on Windows. Using updated models and IP helps mitigate compatibility issues leading to failures.
Running simulations across multiple threads could also cause race conditions and instability. Restricting simulations to single thread avoids these concurrency bugs. Long simulation times with large testbenches also increase likelihood of failures. Breaking down tests and using smaller timesteps is recommended.
Inconsistent Tcl Behavior
Vivado provides Tcl APIs to drive the tool from scripts instead of GUI. But some Tcl commands may exhibit inconsistent behavior or outcomes compared to interactive flows. Tcl puts the IDE in a different state than manual flows causing deviations.
Regenerating Tcl scripts from GUI interactions instead of manually editing resolves some inconsistencies. Sourcing commands after resetting project using ‘close_project’ also improves consistency. Checking return codes and adding error checking helps make scripts more robust.
SDK Issues with Custom Hardware Platforms
The Vivado SDK allows creating embedded software projects based on hardware definitions. Custom platforms require exporting hardware description files from Vivado IP Integrator. However, SDK may fail to automatically resolve IPs and interfaces for complex platforms.
Exporting block designs as ‘Sources’ preserves connectivity details better than ‘IPs’ for SDK. All connected slave interfaces must be exported for successful SDK import. Double checking address maps, interrupts and DSA files avoids obscure link errors when compiling code.
Limited support for ARM-based FPGAs
Although Xilinx promotes the Zynq/Zynq MPSoC ARM+FPGA devices, their support for developing on actual ARM host machines is limited. Most documentation and resources focus on x86 Windows/Linux hosts for these devices instead.
ARM developers may need to experiment more to find compatible versions and workarounds to get started with Zynq/Zynq MPSoC on ARM laptops. Checking community forums helps find fixes for specific OS builds. An x86 VM is recommended when ARM host support is lacking.
Licensing Challenges with Virtual Machines
For added flexibility, some users run Vivado inside virtual machines on Windows hosts. This allows quick recovery using VM snapshots when issues arise. However, Vivado’s licensing checks may fail when run inside VMs due to vendor ID mismatches.
The VM vendor ID must match the physical system vendor ID for the license server to authorize properly. Passing through the USB dongle instead of remoting avoids this issue. Validating VM configurations before purchase is advised to prevent licensing headaches.
Insufficient Performance on Low-End Systems
Vivado requires significant compute resources for the synthesis, placement and routing operations. Entry-level laptops or old workstations often lack the necessary horsepower to run Vivado optimally leading to slow performance.
Reducing optimization constraints and using minimal device resources can improve experience on lower spec systems. But large designs require high-end processors and lots of RAM for acceptable performance. Upgrading to better hardware or using cloud workstations may be necessary.
In summary, Vivado offers a sophisticated workflow for building and verifying FPGA-based systems on Windows. But developers may face technical challenges, especially when getting started. Following best practices and guidelines tailored for Windows environments can help minimize frustrations when working with Vivado and ARM hardware.
