Graham Kruk

156 Articles

Flash Patch and Breakpoint Unit (FPB) in Arm Cortex-M Explained

The Flash Patch and Breakpoint (FPB) unit in Arm Cortex-M processors provides an efficient mechanism to rewrite flash memory contents…

Graham Kruk 11 Min Read

Arm

Memory Map Regions and Access Behavior in Cortex-M3

The Cortex-M3 memory map is divided into several regions, each with specific access behaviors. The Code region stores program instructions…

Graham Kruk 12 Min Read

Arm

Bit Band and Bit Band Alias Areas in Cortex-M3 Memory

The Cortex-M3 processor has a feature called Bit Banding that allows each individual bit in a word of memory to…

Graham Kruk 8 Min Read

Arm

Bit-band Regions in Arm Cortex (Explained)

Bit-banding is a feature in some Arm Cortex processors that allows single bit modifications to be made to memory mapped…

Graham Kruk 8 Min Read

Arm Cortex M3

Relocating the Vector Table in Cortex-M3 Boot Code

The Cortex-M3 vector table contains the reset value and exceptions handlers that are executed when specific events occur. By default,…

Graham Kruk 8 Min Read

Arm Cortex M3

Using Processor-Only vs. Full Reset in Cortex-M3 Debugging

When debugging Cortex-M3 processors, developers have the option of using either a processor-only reset or a full reset. The choice…

Graham Kruk 11 Min Read

Arm Cortex M3

Managing Reset Domains in Cortex-M3 Systems

The Cortex-M3 processor contains multiple reset domains that allow independent reset control of different modules within the system. Proper configuration…

Graham Kruk 9 Min Read

Arm

Why is there rotate right but not rotate left instruction in cortex m3?

The Cortex-M3 processor implements the ARM Thumb-2 instruction set architecture, which includes 16-bit and 32-bit instructions. The 16-bit instruction set…

Graham Kruk 9 Min Read

Arm

Arm’s Compare and Branch Instructions (CBZ and CBNZ) Explained

The ARM Cortex series of chips support conditional execution of instructions using the Compare and Branch instructions CBZ and CBNZ.…

Graham Kruk 8 Min Read

Arm

Understanding Indirect Branches on Arm with BX and BLX

Indirect branching allows jumping to an address stored in a register, providing flexibility in control flow. The Arm instruction set…

Graham Kruk 7 Min Read

Arm

ARM Program Status Registers

The ARM Program Status Registers (PSRs) are special purpose 32-bit registers that control and reflect the state of the processor.…

Graham Kruk 15 Min Read

Arm Cortex M4

Techniques for Dealing with SysTick’s 24-bit Counter (Cortex-M4)

The 24-bit SysTick counter in Cortex-M4 can be tricky to handle due to its limited range. Here are some techniques…

Graham Kruk 6 Min Read

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