Arm sleep-on-exit is a power saving feature in ARM processors that allows the processor to enter a low power sleep state when exiting certain operations. When enabled, this feature can reduce overall power consumption of ARM-based devices.
What is Sleep Mode?
Sleep mode, also known as low power or standby mode, is an operating state where a processor consumes very little power but can quickly resume normal operation. The processor clock stops and most peripherals are shut down, but the processor state and memory contents are maintained. This allows the system to conserve energy when it is idle but doesn’t need a full restart when activity resumes.
ARM processors support multiple levels of sleep modes, from shallow sleep states that allow fast wakeup but use more power, to deep sleep states that use minimal power but have higher latency when resuming operation. The ARM architecture defines standard sleep modes like Wait for Interrupt (WFI) and Wait for Event (WFE) that processors can enter to reduce power draw during idle periods.
What is Sleep-On-Exit?
Sleep-on-exit is a feature of some ARM processors that allows the processor to automatically enter a sleep state when exiting certain operations, without software explicitly instructing it to sleep. For example, after completing an intensive calculation and returning from an exception handler, the processor can go right into a sleep state without waiting for or requiring any additional sleep instruction from software.
This behavior minimizes the idle time between activities where the processor is awake but not actively doing work. By sleeping immediately at opportune times, overall energy usage is reduced. Sleep-on-exit provides an easy way for systems to take advantage of sleep states without complex software management.
ARM Operations that Support Sleep-On-Exit
Sleep-on-exit can trigger when exiting from:
- Exceptions and interrupts – After handling an exception or interrupt, the processor can sleep instead of waking up to idle state
- Returns from function calls – Upon return from a subroutine or function call, the processor can sleep before continuing program execution
- Instruction synchronization barriers – When reaching checkpoints set by ISB or DSB instructions, sleep can occur before subsequent instructions execute
- WFE wake events – After waking up from a WFE sleep state, can re-enter WFE immediately if no events are pending
The processor looks at specific enable bits and sleep settings to determine whether to actually sleep for each case. Software developers can control which operations induce sleep-on-exit by configuring those bits appropriately for their application.
Benefits of Sleep-On-Exit
The main benefits of the sleep-on-exit feature are:
- Reduced power consumption – By sleeping opportunistically without software overhead, power draw is minimized during idle periods
- Easier integration of sleep states – Hardware automatically handles sleeping, reducing software complexity
- Quicker reaction time – Sleep occurs with little delay after idling, increasing time spent in low power states
- Compatibility across software stacks – Sleep behavior is hardware-controlled, so benefits non-OS and RTOS environments as well
For power-constrained ARM devices like smartphones, Internet of Things nodes, and wearables, the sleep-on-exit feature can provide substantial energy savings. It also simplifies integrating power management since low level hardware handles automatically sleeping.
Controlling and Configuring Sleep-On-Exit
ARM processors provide various control and configuration options to enable software to fine tune sleep-on-exit behavior for their specific performance and power needs.
Sleep-On-Exit Control
The ARM System Control Register (SCR) contains enable bits for the major sleep-on-exit triggers:
- EA bit – Enables sleep-on-exit after handling exceptions and interrupts when set to 1
- NAPI and DAPI bits – Enable sleep-on-exit after normal returns and return from debug state when set
- FWB bit – Allows waiting for write buffers to drain before sleep after DSB when set
Setting these bits allows software to selectively enable the desired sleep-on-exit behaviors in the hardware.
Sleep State Configuration
Properties of the sleep state entered on exit can also be configured:
- SleepDeep bit – Controls whether shallow or deep sleep is used
- SleepType bits – Specify which standard sleep state (WFI, WFE, etc) is entered
This allows balancing power savings versus wakeup latency as needed for the use case.
Interrupt Masking
Individual interrupts can be masked to prevent triggering immediate wakeup after sleep-on-exit. This allows peripherals to be selectively disabled to prolong the sleep state.
Usage Considerations
Some design considerations when utilizing sleep-on-exit include:
- Balancing low power with wakeup latency constraints
- Managing interrupt sources to prevent premature wakeups
- Accounting for energy and timing impacts in performance-critical code sections
- Handling peripherals and hardware that require careful power sequencing
- Testing sleep-on-exit thoroughly across expected use cases
With careful configuration tuning for a particular system’s needs, sleep-on-exit can enable power-efficient designs without extensive software overhead.
Example Implementation
Here is an example code snippet showing how sleep-on-exit could be implemented on an ARM Cortex-M processor for low power: // Enable sleep-on-exit interrupts in SCR SCR |= SCR_SEVONPEND; // Configure desired sleep state SCR &= ~SCR_SLEEPDEEP; // Shallow sleep SCR |= SCR_SLEEPWFE; // Use WFE state // Mask unwanted interrupts __NVIC_DisableIRQ(IRQn_UART1); // Enter low power section __DSB(); __WFE(); __NOP(); // Wakes on event // Processor automatically sleeps on above WFE exit // Do work… // On function return, sleeps again due to NAPI
This allows the processor to automatically sleep when idling, both after the WFE and at function return, without requiring explicit sleep instructions.
Conclusion
The sleep-on-exit feature provides an effective way to reduce power consumption in ARM systems by transparently sleeping whenever the processor becomes idle. Careful configuration allows tailoring sleep behavior to match performance requirements. By enabling intelligent power management in hardware, sleep-on-exit simplifies sleeping implementations across a wide range of software environments.
