ARM processors are based on the ARM architecture developed by ARM Holdings. ARM stands for ‘Advanced RISC Machine’ and was originally developed as a 32-bit RISC (Reduced Instruction Set Computer) processor architecture. Since then, ARM has evolved into a set of architectures including both 32-bit and 64-bit designs.
The key features of ARM processors include:
- RISC design – simpler instructions that can execute within a single clock cycle
- Load/store architecture – operations are performed on registers, not directly on memory
- Fixed-length 32-bit instruction set
- High code density achieved by simple instructions
- Fewer transistors needed compared to complex instruction set (CISC) chips
- Excellent power efficiency due to simpler design
ARM Processing Cores
The ARM architecture defines the basic CPU operation, instruction set and programming model. ARM Holdings then licenses out the architecture to semiconductor companies who design specific ARM-based cores and processors. Some of the major ARM processing cores include:
- Cortex-A Series – Application processors for devices like smartphones, tablets, TVs, cars
- Cortex-R Series – Real-time processors for industrial equipment, robotics, automotive
- Cortex-M Series – Microcontroller units for embedded and IoT devices
Each series is further divided into specific cores optimized for different performance/power requirements like the high-performance Cortex-A76 or the power-efficient Cortex-M3 core.
ARM Register Bank and Program Status Registers
The ARM architecture defines 31 general purpose 32-bit registers labeled R0 to R30. These registers are used to store data for processing as well as memory addresses. There is also a Current Program Status Register (CPSR) which stores condition code flags and the current processor mode bits.
The CPSR stores important status and control information like:
- Processor operation mode – user, system, privileged, etc
- Instruction set state – ARM or Thumb
- Condition code flags – for results of operations
- Interrupt disable bits – to mask interrupts
In addition to the CPSR, there are Saved Program Status Registers (SPSRs) to save previous CPSR contents when switching operation modes.
ARM Instruction Set
The ARM instruction set provides simple and predictable instructions that can be executed within a single clock cycle. Most instructions are 32 bits long. The key types of instructions in the ARM instruction set include:
- Data Processing – Arithmetic, logical, and move operations on registers or immediates
- Load/Store – Transfer data between registers and memory
- Flow Control – Branching and function call instructions
- Supervisor Call – Requests privileged operations like I/O or OS functions
The ARM architecture uses conditional execution for most instructions based on the status flags. This avoids having to use branch instructions for simple conditional code sequences.
For improved code density, ARM also supports a compressed 16-bit Thumb instruction set. Cortex-M series cores use Thumb-2 technology that provides a mix of 16-bit and 32-bit Thumb instructions.
ARM Operating Modes and Privilege Levels
The ARM architecture defines different processor modes to support operating system functions and protection mechanisms. The current mode is stored in the CPSR register. The main modes are:
- User (usr) – Unprivileged mode for normal applications
- FIQ (fiq) – Supports fast interrupts with very low latency
- IRQ (irq) – Used for general-purpose interrupt handling
- Supervisor (svc) – Provides protected access to limited system resources
- Abort (abt) – Entered on data or instruction faults
- Undefined (und) – Undefined instruction handler mode
- System (sys) – Privileged operating system tasks
This mode system allows the operating system kernel to run in a privileged system mode while applications run unprivileged user mode. Modes like FIQ, IRQ and Abort handle different types of exceptions and interrupts.
ARM Memory and Addressing Modes
ARM processors use a load/store architecture where data processing operations are performed on registers, not directly on memory. Instructions must load data from memory into registers before operating on them.
The ARM architecture supports flexible memory addressing modes for load/store instructions:
- Offset – Register + offset value
- Pre-indexed – Register + offset, writeback
- Post-indexed – Register, writeback register + offset
This allows efficiently accessing memory with auto-incrementing or auto-decrementing addresses. ARM also uses banked registers to quickly switch contexts in different processor modes.
ARM Coprocessors and Multiprocessing
The ARM architecture provides coprocessor support for extending the instruction set with specialized processing capabilities like graphics, DSP, cryptography, etc. Coprocessors have their own dedicated registers.
ARM also supports symmetric multiprocessing (SMP) where multiple identical processors share memory and I/O resources. Cortex-A series processors implement SMP for high-performance multi-core processors used in devices like smartphones and tablets.
ARM processors also utilize SIMD (single instruction multiple data) instructions present in various versions like NEON, SVE, SVE2, etc. This allows parallel data processing on multiple data elements using a single instruction.
ARM Licensing and Platforms
As a core IP architecture licensor, ARM partners with major chip companies to integrate ARM cores into full-featured processors and SoC (System-on-Chip) designs. These chips go into billions of devices and platforms including:
- Smartphones – Snapdragon, Exynos, MediaTek Dimensity
- Tablets – Bionic, Exynos, Dimensity
- Embedded systems – Microchip, NXP i.MX, Renesas R-Car
- Wearables – Qualcomm, Samsung, MediaTek
- Servers – Amazon Graviton, Ampere Altra, Fujitsu A64FX
The broad ecosystem support for ARM combined with its power efficiency and customizability has made it the most popular commercial processor architecture, powering over 95% of smartphones and a growing share of other segments.
