The ARM Cortex-M3 is a 32-bit ARM processor core licensed by ARM Holdings. It is aimed at embedded applications requiring a low power, low cost and high performance microcontroller. The Cortex-M3 offers significantly higher DSP performance than previous Cortex-M cores, making it well suited for a wide range of embedded applications.
Key Features
- 32-bit ARMv7-M architecture
- 3 stage pipeline
- Thumb-2 instruction set
- Embedded Trace Macrocell (ETM) for instruction trace
- Memory Protection Unit (MPU)
- Nested Vectored Interrupt Controller (NVIC)
- Hardware divide instruction
- Optional floating point unit (FPU)
Architecture
The Cortex-M3 implements the ARMv7-M architecture which is a stripped down version of the ARMv7 architecture for microcontroller applications. It includes Thumb-2 technology for improved code density compared to previous Thumb instruction sets. The three stage pipeline comprises Fetch, Decode and Execute stages.
Registers
The Cortex-M3 has 16 32-bit general purpose registers, R0-R15. These can be accessed as either 32-bit or 16-bit registers to allow backward compatibility with Thumb and Thumb-2 code. There is also a program counter (PC), link register (LR) and program status register (PSR). The PSR contains condition flags, interrupt enable bits and the current processor mode.
Operating Modes
The processor supports seven operation modes to provide different access levels and stack pointers:
- User (unprivileged) mode
- Privilege mode
- Supervisor mode
- Abort mode
- Undefined mode
- IRQ mode
- FIQ mode
This allows the operating system kernel to run in a privileged mode while applications run in user mode. Interrupt handlers run in IRQ, FIQ or privilege mode depending on the interrupt type.
Memory System
The Cortex-M3 supports a Von Neumann architecture with a unified address space for code and data. It has a Harvard architecture style bus interface with separate instruction and data buses. This allows instruction and data accesses to occur in parallel.
The memory system includes instruction and data tightly coupled memories, cache, write buffer and external bus interface unit. Tightly coupled memories provide low latency access for time critical code and data. The optional cache reduces accesses to slower external memory.
Exceptions
The Nested Vectored Interrupt Controller (NVIC) provides low latency exception handling for interrupts and exceptions. There are 240 interrupt sources which can be individually enabled or disabled. The exception model allows late arrival of interrupts to be pended until the current instruction completes execution.
Debug Support
The Embedded Trace Macrocell (ETM) provides instruction and data trace capabilities for debugging. Trace data can be output over a serial wire or stored on-chip for later analysis. The ETM provides program counter and data tracing with timestamping to allow reconstruction of program flow and data manipulation.
The embedded debug module (EDM) facilitates run control, breakpoints and watchpoints. It uses the ARM Debug Access Port (DAP) for debug probe connectivity. The DAP provides JTAG or serial wire (SWD) interface options.
Memory Protection Unit
The optional Memory Protection Unit (MPU) provides support for protected memory regions. Each MPU region can be configured with access permissions of no access, read-only or read-write. This prevents privileged software from corrupting application data accidentally.
Floating Point Unit
The optional floating point unit (FPU) provides hardware acceleration for floating point arithmetic instructions. It supports both single precision (32-bit) and double precision (64-bit) operations.
Instruction Set
The Cortex-M3 implements the Thumb-2 instruction set which includes both 16-bit and 32-bit instructions to provide good code density. 16-bit Thumb instructions execute in a single cycle while 32-bit instructions can take 1-3 cycles depending on pipeline interlocks.
Key features of the Thumb-2 instruction set include:
- 16-bit and 32-bit instructions
- Uniform register access in 32-bit and 16-bit instruction types
- Load/store architecture with post-increment addressing
- Conditional execution of most instructions
- Extensive branch instructions including branch with link
- Powerful shift and bit field manipulation instructions
- Saturating arithmetic and rounding instructions
- Hardware divide instruction
- Optional single and double precision floating point (VFPv3)
The combination of 16-bit and 32-bit instructions provides good performance together with high code density, reducing memory requirements. The comprehensive instruction set allows efficient C and assembly language compilation with minimal need for workarounds.
Development Tools
The Cortex-M3 processor can be targeted using ARM’s own toolchain comprising:
- ARM Compiler toolchain for C/C++
- ARM Assembler
- ARM Linker
- ARM Development Studio IDE
Many third party compilers and IDEs also support the Cortex-M3 including GCC, IAR and Keil. Debuggers that support the ETM trace and EDM debug modules are available.
Example Devices
The Cortex-M3 processor core is widely deployed in microcontroller devices across many manufacturers. Example devices include:
- NXP LPC1700
- STM32F103
- TI Stellaris LM3S
- Atmel SAM3
- Silicon Labs EFM32
These microcontrollers incorporate the Cortex-M3 core together with memories, peripherals and interfaces to create complete system-on-chip solutions for embedded applications.
Summary
The ARM Cortex-M3 offers an optimal combination of performance, power efficiency and cost for a wide range of embedded systems. Key features including Thumb-2 instruction set, nested interrupts and optional memory protection provide a flexible architecture for high performance microcontroller applications.
