The ARM Cortex-M0+ processor is a 32-bit reduced instruction set computing (RISC) processor designed for embedded and Internet of Things (IoT) applications. It is an ultra-low-power microcontroller CPU that is highly energy-efficient while still providing good performance for basic tasks.
Overview
The Cortex-M0+ is part of ARM’s Cortex-M series of embedded processors. It is their smallest and simplest processor aimed at low-cost and low-power embedded applications that only require basic compute capabilities. Compared to other Cortex-M processors like the M3 and M4, the M0+ has a reduced feature set optimized for simplicity and efficiency.
Key features of the Cortex-M0+ processor include:
- 32-bit RISC architecture
- Up to 48MHz clock frequency
- 2-stage pipeline
- 32-bit registers
- Load/store architecture
- Thumb instruction set
- Single-cycle GPIO access
- Memory Protection Unit (MPU)
- Wake up interrupt controller (WIC)
- ARMv6-M Thumb instruction set
- 3-cycle multiplier
- Hardware divide instructions
The Cortex-M0+ is a dual-issue superscalar processor meaning it can complete up to two instructions per clock cycle. This helps improve performance while keeping the design simple and power-efficient. It has a two-stage pipeline that enables quick instruction execution.
One key characteristic of the M0+ is its ultra low power consumption. Static power is under 3uA/MHz and dynamic power is about 9uA/MHz. This makes it highly suited for battery-powered and energy harvesting applications.
Architecture
The ARM Cortex-M0+ is a 32-bit reduced instruction set (RISC) processor. It uses the Thumb-2 instruction set which is a compressed variant of the ARM instruction set optimized for embedded applications. The Thumb-2 instruction set provides a balance between code density, performance, and complexity.
The M0+ is a load/store architecture meaning data operations only occur between registers and memory. Computations occur using the contents of registers as operands. This differs from some CISC processors that allow operations directly on memory contents.
Some key architectural aspects of the Cortex-M0+ include:
- 3-stage pipeline – Fetch, Decode, Execute
- 32-bit registers – 16 general purpose registers
- Memory Protection Unit (MPU) – provides memory access control
- Single-cycle GPIO – fast IO access
- Wake Up Interrupt Controller (WIC) – manages wake up from sleep/low power
- Nested Vectored Interrupt Controller (NVIC) – handles interrupt management
- SysTick timer – 24-bit system timer
The pipeline is simplified compared to more complex ARM processors. Having only 3 stages (fetch, decode, execute) reduces power consumption while still providing good performance for a low-power microcontroller.
The general purpose registers play a key role in the architecture. Not only are they used for data computation, but they also store stack pointers, program counter, and link registers. There are 13 usable general purpose registers (R0-R12) plus three special purpose (stack pointer, link register, program counter).
Memory and Peripherals
The Cortex-M0+ supports both internal and external memory for program and data storage. Typical internal memory consists of up to 256KB of flash memory for holding programs and up to 32KB of SRAM for data. External memory support includes interfacing to external flash, SRAM, and ROM chips.
Peripheral interfaces are built into the Cortex-M0+ processor to allow connecting various external devices. Common peripherals include:
- General purpose I/O ports – GPIO pins for buttons, LEDs, etc.
- Timers – timer/counter blocks for timekeeping and PWM
- Serial interfaces – UART, SPI, I2C
- Analog to Digital Converters – for reading analog sensors
- Digital to Analog Converters – for controlling outputs
- Touch sensing – capacitive touch capabilities
- External bus interface – connect external memories and devices
The inclusion of these common peripherals on chip helps reduce overall system cost and complexity. Rather than interfacing separate external chips, the peripherals are integrated with the CPU core allowing more compact and efficient designs.
Power Management
A key feature of the Cortex-M0+ is the use of multiple power saving techniques to enable ultra low power operation. These power saving modes allow the processor to be extremely energy efficient in embedded and battery-powered designs.
Some of the power saving modes supported include:
- Sleep Mode – CPU stopped, peripherals running, fast wake up
- Deep Sleep Mode – Clocks gated off, only WIC active, slow wake up
- Standby Mode – Supply voltage reduced, backup SRAM retention
- Shutdown Mode – All power removed except wakeup logic
In sleep mode, the CPU core can be shut down while keeping peripherals and memory active. This allows peripheral operation to continue while saving CPU power. Deep sleep gates off clocks and shuts down peripherals and non-backup memory. Only the WIC remains active to allow wake up from external interrupts.
Standby mode uses an integrated voltage regulator to reduce the supply voltage while maintaining the contents of backup SRAM and wakeup logic. Shutdown mode removes power entirely except for logic needed to restart the processor.
Optimizing and utilizing these different low power modes allows Cortex-M0+ based systems to operate for long periods on battery power. Typical consumption can range from just 3uA while sleeping up to only 9uA/MHz when active, enabling many low-power use cases.
Use Cases
The Cortex-M0+ targets cost sensitive and power constrained embedded applications. Its combination of compact size, good performance, and ultra low power make it well suited for a variety of IoT edge devices. Some example uses include:
- Wearable devices – fitness trackers, smartwatches
- Wireless sensors – environmental monitoring, infrastructure
- Smart home devices – sensors, controllers, automation
- Industrial – motor control, metering, asset tracking
- Medical – blood pressure, glucose monitors, infusion pumps
- Consumer – remotes, cameras, appliances
The Cortex-M0+ can serve as the control processor managing basic system tasks in each of these devices. Its peripherals allow interfacing to various sensors to collect data and communicate results. Low power operation enables long battery life.
The M0+ is not well suited for application processors in smartphones or computationally intensive applications. Its goal is simple embedded microcontroller tasks rather than high performance. There are higher performance Cortex-M processors such as the M3, M4, and M7 for applications needing greater processing capability.
Development Tools
The Cortex-M0+ processor can be programmed using ARM’s MDK-ARM or GCC toolchains. These include C/C++ compilers, debuggers, and software libraries tailored for the M0+ and Thumb-2 instruction set. The ARM Mbed operating system is also commonly used with M0+ processors for quick development.
Various development boards are available from ARM and its partners containing example M0+ SoC chips. These provide an easy way to evaluate the processor and start software development. Onboard peripherals like LEDs, buttons, displays and connectors enable interfacing external hardware.
Some common development boards using the Cortex-M0+ include:
- NXP LPC11U24
- STM32 Nucleo-32 boards
- Maxim MAX32600MBED
- Silicon Labs EFM32 Giant Gecko
- Nordic nRF51822
These development kits allow exploring the unique features of the M0+ architecture including power management, efficient Thumb-2 instructions, single-cycle IO, and integrated peripherals. The boards can be used to start prototyping and designing an end product.
Summary
The ARM Cortex-M0+ is an efficient 32-bit embedded processor optimized for simple microcontroller applications. Key characteristics include:
- Ultra low power – as low as 3uA static and 9uA/MHz active current
- Up to 48 MHz operation
- 2 stage pipeline with streamlined architecture
- Thumb-2 instruction set balances code density and performance
- Load/store architecture uses registers for computation
- Integrated peripherals reduce system cost and size
- Variety of power saving modes enable long battery life
With its careful balance of simplicity, efficiency, and features, the Cortex-M0+ brings 32-bit computational capabilities to low-cost, low-power embedded devices. It serves as the control processor in a wide range of IoT and edge designs.
