The Arm Cortex-M0+ processor is an ultra low power 32-bit microcontroller CPU core designed for use in energy-constrained devices. With advanced power saving features and an efficient RISC architecture, the Cortex-M0+ enables extremely low power consumption suitable for battery-powered and energy harvesting applications.
Some of the key attributes of the Cortex-M0+ architecture that enable its low power operation are:
- Single-cycle I/O – Allows fast IO transactions with minimal power
- Up to 15 channels event system – Helps reduce power by waking the processor only when needed
- Wake up interrupt controller – Further reduces power by allowing peripherals to wake the CPU themselves
- Low interrupt latency – Minimizes time spent servicing interrupts
- Up to 8 sleep modes – Optimizes power for different use cases
- Voltage scaling – Dynamically adjusts voltage and frequency
Active Power Consumption
When the Cortex-M0+ is actively running code and instructions, its power consumption depends primarily on its operating voltage and frequency. Lower voltages and frequencies will result in lower active power.
For example, when running at 1.8V and 24MHz, typical active power consumption is around 600μA/MHz. This equates to around 14mA when fully active. Lowering the voltage to 1.2V cuts the active power in half to around 300μA/MHz or 7mA when running at 24MHz.
In terms of benchmarks, the CoreMark-PRO score for Cortex-M0+ is about 0.7 CoreMarks/MHz. For a chip running at 24MHz, this translates to a score of around 16.8. Higher speeds and voltages will increase both the power and performance.
Sleep Mode Power
To save power when inactive, the Cortex-M0+ supports multiple sleep modes that shut down parts of the core and peripherals. Lower power sleep modes exist at the expense of higher wake-up latency.
The lightest sleep mode is sleep mode 0 which simply gates the CPU clock while keeping everything else running. This mode has the fastest wake-up but still reduces power by 30-50% typically.
Deeper sleep modes progressively shut down more parts of the chip. For example, sleep mode 1 powers off the flash memory and sleep mode 2 powers down peripherals. In the deepest mode 4, almost everything is powered off except the watchdog timer.
Sleep mode 4 can result in power consumption down in the single digit μA range, over 1000x less than active power. The tradeoff is wake-up latency up to a few milliseconds. Proper mode selection ensures minimal power without sacrificing responsiveness.
Clock Gating
In addition to the sleep modes, the Cortex-M0+ employs extensive clock gating to prevent power from being wasted in unused sub-systems. This allows parts of the core like the memory interfaces or DSP extension to be powered down independently when not active.
Smart use of clock gating is a key enabler of the Cortex-M0+’s low power. For example, the memory interface clocks can automatically gate based on the bus activity. Peripherals like timers and watchdog include clock gating registers to disable clocking when idle.
Voltage Scaling
Scaling the supply voltage is one of the most effective ways to reduce power on the Cortex-M0+. Lower voltages quadratically decrease the dynamic power needed for computation. The Cortex-M0+ can operate down to 1.2V in most process nodes.
Dynamic voltage scaling allows voltage to be adjusted on the fly based on the performance needs at a given moment. When full speed is not required, the voltage can be reduced to save power. The voltage is then increased again when required.
Adaptive voltage scaling monitors the logic load to automatically adjust voltage to the minimum level required. This provides power savings with no software overhead. External power management ICs enable advanced voltage scaling techniques.
Energy Efficient Design
Several architectural optimizations make the Cortex-M0+ inherently energy efficient for ultra low power applications:
- Single cycle 32-bit multiply accumulate – Reduces computation cycles
- Thumb-2 instruction set – High code density reduces memory accesses
- Up to 15 wake-up interrupts – Minimizes idle time
- Nested vectored interrupt controller – Quickly services interrupts
- Peripherals use low power modes when idle
- Event system turns on peripherals only when needed
In summary, through an optimized RISC architecture, multiple sleep modes, extensive clock gating, voltage scaling and energy efficient design, the Arm Cortex-M0+ achieves exceptionally low power consumption making it an ideal choice for energy-constrained embedded applications.
